1. Field
This patent document relates to a semiconductor device, and more particularly, to a three-dimensional (3D) nonvolatile memory device.
2. Description of the Related Art
A nonvolatile memory device maintains its stored data even without a constant source of power. Recently, the improvement in integration of two-dimensional (2D) memory devices, which are fabricated in a single layer over a silicon substrate, has reached its limit. Thus, a 3D nonvolatile memory device has been proposed, including memory cells which are vertically stacked over a silicon substrate.
FIG. 1 is a perspective view illustrating a conventional 3D nonvolatile memory device. To simplify the description, interlayer dielectric layers are not illustrated in FIG. 1.
Referring to FIG. 1, the 3D nonvolatile memory device includes a pipe channel PCH, a source-side half channel SCH, and a drain-side half channel DCH. The pipe channel PCH is buried in a pipe gate PG, and the source-side half channel SCH and the drain-side half channel DCH are connected to the pipe channel PCH. The source-side half channel SCH, the pipe channel PCH, and the drain-side half channel DCH form one full channel CH.
The memory device further includes source-side word lines S_WL and drain-side word lines D_WL. The source-side word lines S_WL are stacked while surrounding the source-side half channel SCH, and the drain-side word lines D_WL are stacked while surrounding the drain-side half channel DCH. The source-side word lines S_WL and the drain-side word lines D_WL are extended in parallel to a first direction I-I′. Furthermore, a source select line SSL is provided over the source-side word lines S_WL, and a drain select line DSL is provided over the drain-side word lines D_WL.
At this time, source-side channels SCH of strings ST0 and ST1 adjacent in a second direction II-II′ are commonly connected to one source line SL, and drain-side channels DCH of the strings ST0 and ST1 are commonly connected to one bit line BL.
According to the above-described structure, however, word lines S_WL and D_WL that are narrow in width are stacked high. Thus, the stacked structure of the word lines may tilt. Furthermore, when a memory device is fabricated, stacked interlayer dielectric layers and conductive layers must be etched to form slits between a pair of source-side channel SCH and drain-side channel DCH forming one channel CH that is between the respective channels CH. Thus, the slits have a narrow width, and the difficulty level of the etching process increases. Furthermore, as the integration of the memory device increases, the number of word lines that need to be stacked further increases. Thus, the stacked structure of the word lines may tilt more, increasing the difficult of the etching process.